Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

ABSTRACT

Disclosed are a semiconductor device comprising a capacitor and a double-layer metal contact and a method fabricating the same. The method comprising: forming a gate of a peripheral transistor for a peripheral circuit; forming a first contact and a first peripheral circuit wiring layer pattern on a first interlayer insulating layer; forming a second contact and a second peripheral circuit wiring layer pattern; selectively removing a portion of the second interlayer insulating layer in a cell region; forming a mold layer covering the second peripheral circuit wiring layer pattern; forming storage nodes passing through the mold layer; removing the mold layer; forming a dielectric layer and a plate node, which cover the storage nodes; forming a third interlayer insulating layer; and forming third contacts passing through the third interlayer insulating layer.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. 119(a) to KoreanApplication No. 10-2011-0012900, filed on Feb. 14, 2011, in the KoreanIntellectual Property Office, which is incorporated herein by referencein its entirety as set forth in full.

BACKGROUND

Embodiments of the present invention relate to a semiconductor device,and more particularly, to a semiconductor device comprising a capacitor,a double-layer peripheral circuit wiring line and a double-layer metalcontact, and to a fabrication method thereof.

Many efforts have been made to increase the height of a capacitor so asto maximize capacitance characteristics of the capacitor in a limitedarea of a substrate, thereby increasing a data storage capacity of theDRAM semiconductor device. As the design rule shrinks, the technologynode of DRAM is decreasing. For this reason, it is particularlydifficult not only to ensure the storage capacitance (Cs) to ensure asensing margin when sensing data stored in a storage node, but also toreduce a parasitic bit-line capacitance (Cb).

In technology nodes of 32 nm or below, a dimension of patterns israpidly becoming smaller, thus making it substantially more difficult toutilize cylindrical storage nodes which have conventionally been used.For this reason, efforts have been made to significantly increase theheight of a capacitor to ensure its capacitance characteristics.However, as the capacitor height increases rapidly, a step height afteretching of a plate node also increases rapidly so that the etch processmargin becomes rapidly smaller. Also, in a peripheral region in whichperipheral circuits such as a sense amplifier (SA) are formed, a patternpitch of wiring lines interconnecting the peripheral circuits decreasesrapidly, thus making it difficult to use single patterning to form apattern of the peripheral circuit wiring lines. For this reason, effortshave been made to apply double patterning technology (DPT).

In addition, as the capacitor height increases, the height of a metalcontact (M1C) connecting a peripheral circuit wiring line or a platenode to a metal line (M1) also increases. Also, metal contact holes formetal contacts become deeper, and thus an occurrence of bridges betweenthe metal contact holes increases. As the metal contact holes getdeeper, a size relative to a top of the metal contact holes increases,the interval margin between the metal contact holes gradually narrows,and the amount of oxides that are lost in a cleaning process afterformation of the metal contact holes increases so that the size of theholes increases. As the size of the metal contact holes increases,bridges between the contact holes occur more frequently. If the intervalbetween the metal contact holes is increased in order to overcome theabove-described shortcomings, the area of the peripheral region willincrease due to the increase in the interval together with the increasein the size of the metal contact holes. Therefore the size of the wholedevice chip will increase, thus causing undesired results.

SUMMARY

An embodiment of the present invention relates to a semiconductor deviceincluding a capacitor and a metal contact and a fabrication methodthereof, in which a height of storage nodes can be increased to ensurehigher capacitance, and an occurrence of defects in peripheral circuitwiring lines and metal contacts for peripheral circuits can beeffectively prevented.

In one embodiment, a method for fabricating a semiconductor deviceincluding a capacitor and a double-layer metal contact includes thesteps of: forming a second interlayer insulating layer on a cell regionand a peripheral region; forming a second contact which passes through aportion of the second interlayer insulating layer on the peripheralregion; selectively removing a portion of the second interlayerinsulating layer on the cell region while allowing a portion of thesecond interlayer insulating layer in the peripheral region to remain;forming a mold layer covering both the portion of the cell region fromwhich the second interlayer insulating layer was removed and the secondcontact; forming storage nodes which pass through a portion of the moldlayer in the cell region; selectively removing the mold layer to exposethe storage nodes; forming a dielectric layer and a plate node, whichcover the exposed storage nodes; forming a third interlayer insulatinglayer covering the plate node; and forming third contacts which passthrough the third interlayer insulating layer so as to be connected tothe plate node and the second contact, respectively.

In another embodiment, a method for fabricating a semiconductor deviceincluding a capacitor and a double-layer metal contact includes thesteps of: forming a gate of a peripheral transistor for a peripheralcircuit on a peripheral region of a semiconductor substrate including acell region and the peripheral region; forming a first interlayerinsulating layer covering the gate; forming a first contact and a firstperipheral circuit wiring layer pattern, which are connected to the gateso as to constitute the peripheral circuit; forming a second interlayerinsulating layer covering the first peripheral circuit wiring layerpattern; forming a second contact and a second peripheral circuit wiringlayer pattern, which pass through the second interlayer insulating layerso as to constitute the peripheral circuit; selectively removing theportion of the second interlayer insulating layer on the cell regionwhile allowing the portion of the second interlayer insulating layer inthe peripheral region to remain; forming a mold layer covering both aportion of the semiconductor substrate from which the portion of thesecond interlayer insulating layer was removed and the second peripheralcircuit wiring layer pattern; forming storage nodes which pass through aportion of the mold layer in the cell region; selectively removing themold layer to expose the storage nodes; forming a dielectric layer and aplate node, which cover the exposed storage nodes; forming a thirdinterlayer insulating layer covering the plate node; and forming thirdcontacts which pass through the third interlayer insulating layer so asto be connected to the plate node and the second peripheral circuitwiring layer pattern, respectively.

In another embodiment, the peripheral circuit may include a senseamplifier which senses data to be stored in the storage nodes.

In another embodiment the method for fabricating the semiconductor mayfurther include the steps of: forming bit lines which are insulated by aportion of the first interlayer insulating layer on the cell region; andforming storage node contacts which pass through the first interlayerinsulating layer so as to be connected to the storage nodes,respectively.

In another embodiment, the step of forming the bit lines may include thesteps of: forming damascene trenches in the first interlayer insulatinglayer; and forming the bit lines filling the damascene trenches.

In another embodiment, the step of forming the first peripheral circuitwiring layer pattern may include the steps of: obtaining a layout of theperipheral circuit wiring line for the peripheral circuit; extracting alayout of the first peripheral circuit wiring layer pattern, a layout ofthe second contact and a layout of the second peripheral circuit fromthe layout of the peripheral circuit wiring line; forming a firstcontact hole exposing the gate; forming the first peripheral circuitwiring layer, which fills the first contact hole, on the firstinterlayer insulating layer; and selectively etching the first circuitwiring layer so as to have a configuration corresponding to the layoutof the first peripheral circuit wiring layer pattern, thus forming thefirst contact and the first peripheral circuit wiring layer pattern.

In another embodiment, the step of forming the second peripheral circuitwiring layer pattern may include the steps of: forming the secondcontact hole, which passes through the second interlayer insulatinglayer, so as to have a configuration corresponding to the layout of thesecond contact; forming the second peripheral circuit wiring layer,which fills the second contact hole, on the second interlayer insulatinglayer; and selectively etching the second peripheral circuit wiringlayer so as to have a configuration corresponding to the layout of thesecond peripheral circuit wiring layer pattern, thus forming the secondcontact and the second peripheral circuit wiring layer pattern.

In another embodiment, the step of selectively removing the portion ofthe second interlayer insulating layer on the cell region may includethe steps of: forming on the second interlayer insulating layer a maskpattern for exposing the cell region; and selectively etching out aportion of the second interlayer insulating layer exposed through themask pattern.

In another embodiment, the method may further include a step of formingat an interface between the mold layer and the remaining secondinterlayer insulating layer an etch stopper extending to cover thesecond peripheral circuit wiring layer pattern, in which the etchstopper may protect the second interlayer insulating layer when the moldlayer is removed.

In another embodiment, the step of forming the dielectric layer and theplate node may include the steps of: forming layers for the dielectriclayer and the plate node so as to extend onto the etch stopper exposedby removal of the mold layer; and selectively etching out the portion ofthe dielectric layer for the plate node, which overlaps with theremaining portion of the second interlayer insulating layer, thuspatterning the plate node, in which the third contacts which areconnected to the plate node may be located on the remaining portion ofthe second interlayer insulating portion.

In another embodiment, the method may further include a step of formingon the mold layer a support layer for supporting the storage nodes.

In one embodiment, a semiconductor device including: a cell region and aperipheral region; storage nodes formed in the cell region; a secondcontact passing through a second interlayer insulating layer formed onthe peripheral region; a dielectric layer and a plate node, which coverthe storage node and of which the end extends onto the second interlayerinsulating layer; a third interlayer insulating layer covering the platenode and the second interlayer insulating layer; and third contactswhich pass through the second interlayer insulating layer so as to beconnected to both a portion of the plate node on the second interlayerinsulating layer and the second contact, respectively.

In another embodiment, a semiconductor device may include: asemiconductor substrate including a cell region and a peripheral region;a peripheral transistor and a gate, which are formed on the peripheralregion of the semiconductor substrate to constitute a peripheral region;a first interlayer insulating layer formed to cover the gate; a firstcontact and a first peripheral circuit wiring layer pattern, which areformed on a portion of the first interlayer insulating layer on theperipheral region so as to be connected to the gate and to constitutethe peripheral circuit; a second interlayer insulating layer formed onthe peripheral region to cover the first peripheral circuit wiring layerpattern; a second contact and a second peripheral circuit wiring layerpattern, which are formed to pass through the second interlayerinsulating layer so as to constitute the peripheral circuit; storagenodes formed on a portion of the first interlayer insulating layer onthe cell region; a dielectric layer and a plate node, which cover thestorage nodes and of which the end extends onto the second interlayerinsulating layer; a third interlayer insulating layer covering the platenode and the second interlayer insulating layer; and third contactswhich pass through the second interlayer insulating layer so as to beconnected to both a portion of the plate node on the second interlayerinsulating layer and the second peripheral circuit wiring layer pattern,respectively.

In another embodiment, the peripheral circuit may include a senseamplifier that senses data to be stored in the storage nodes.

In another embodiment, the semiconductor device may further include anetch stopper which is formed at an interface between the second andthird interlayer insulating layers and extends onto the first interlayerinsulating layer to support the sides of a lower portion of the storagenode and to isolate the storage nodes from the second interlayerinsulating layer.

In another embodiment, the height of the second contact may be 45-70% ofthe height of the storage node.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and other advantages will be moreclearly understood from the following detailed description taken inconjunction with the accompanying drawings, in which:

FIGS. 1 to 4 show layouts of peripheral circuit wiring lines forperipheral circuits according to an embodiment of the present invention;and

FIGS. 5 to 14 are cross-sectional views showing a semiconductor devicecomprising a capacitor and a double-layer metal contact according to anembodiment of the present invention, and a method for fabricating thesemiconductor device.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Hereinafter, embodiments of the present invention will be described withreference to the accompanying drawings. However, the embodiments are forillustrative purposes only and are not intended to limit the scope ofthe invention.

An embodiment of the present invention proposes a method of ensuring thecapacitance of a capacitor by forming storage nodes having increasedheight in a substrate area which is limited as a result of a rapidreduction in the design rule of semiconductor devices. In addition,according to an embodiment, peripheral circuit wiring lines, such as afirst metal layer (MT0), which are substantially impossible to form by asingle patterning process, are formed of a double layer consisting oftwo layers without using a double patterning technology (DTP) processwhich cannot ensure an adequate patterning margin. The upper and lowerlayers of the double layer for the peripheral circuit wiring lines areconnected to each other by a metal contact (second M0C) to constituteperipheral circuits such as a sense amplifier (SA).

As used herein, the term “MTO” refers to a peripheral circuit wiringlayer that connects peripheral circuit transistors, formed in theperipheral region of a DRAM device, to constitute peripheral circuitssuch as SA or a sub-word driver (SWD). The term “M0C” refers to aninterconnection contact that connects the peripheral circuit wiringlayer with the peripheral transistors. In a DRAM device metal wiringlines, each generally consisting of two layers mean a first metal wiringline (M1) and a second metal wiring line (M2), and a metal contactconnecting M1 with M0C is referred to as M1C. In an embodiment of thepresent invention, when MT0 consisting of two layers are introduced, thesecond MT0 that is the second layer is formed at about half of theheight of a storage node (SN), thus increasing the patterning margin ofM1C.

Considering the patterning margin of the second M0C formed byintroducing the second MT0 as the second layer and the patterning marginof M1C, the MT0 layer is formed at about half of the height of SN, adepth of M1C can be increased so that an increase in a dimension of thecontact holes can be prevented, thus preventing the occurrence of abridge between the contact holes. Herein, the second M0C can have arelatively large pitch, and thus even when the depth of a contact holefor the second M0C is increased, there is no substantial loss in thepatterning margin, and thus the height of the second MT0 can beincreased. Also, because the level of the second MT0 can be elevated tohalf of the height of an SN, the step height of a plate node (PN) can bereduced to increase the patterning margin of the PN. Thus an M1C that isconnected to the plate node can become closer to the cell region, thusreducing the design rule to reduce the chip size of the semiconductordevice. In addition, after patterning of the second MT0, a siliconnitride layer (Si₃N₄) for stopping the etching of SN is formed to fillbetween MT0s, whereby a punch phenomenon resulting from the misalignmentof M1C and MT0 can be inhibited.

In an embodiment of the present invention, the first MT0 layer isreferred to as the “first peripheral circuit wiring layer”, the secondMT0 as the “second circuit wiring layer”, the first M0C as “the firstcontact”, the second M0C as the “second contact”, and the M1C as the“third contact”.

FIGS. 1 to 4 show layouts of peripheral circuit wiring lines forperipheral circuits according to embodiments of the present invention.

Referring to FIG. 1, peripheral circuits may be circuits for sensing thedata stored in memory cells, such as a sense amplifier (SA). Theperipheral circuits may be integrated in a peripheral region to order tocontrol an operation of memory cells integrated in a cell region of asemiconductor device such as a DRAM memory device. The memory cell maycomprise a cell transistor formed at an intersection between a bit lineand a word line. The memory cell may also comprise a capacitorcomprising storage nodes for storing data, the capacitors may beconnected to a source of the cell transistor.

A SA that reads out data stored in a storage node may be a circuitcomprising peripheral circuit wiring lines connecting peripheraltransistors to each other, where the peripheral transistors may beformed in a peripheral region. Such peripheral circuit wiring lines areformed of patterns having a wiring line layout 10 as shown in FIG. 1.For 30-nm technology node DRAM devices, a pattern pitch of theperipheral circuit wiring lines may be set at 73 nm based on a minimumpitch. The first metal contact (M1C) is connected to the first metalwiring line (M1). Herein, if the height of the storage node of acapacitor is 22000 Å or higher in order to ensure the capacitance of thecapacitor, the depth (or height) of M1C will correspond to the height ofthe storage node. If an interlayer insulating layer having a thicknessof about 4000 Å is added thereto, the height of the storage node willincrease to about 26000 Å. When a contact hole for this deep M1C isformed by etching, the sidewall profile of the contact hole is inclinedin order to ensure etching properties and the opening of the bottom.Thus the interval between adjacent M1Cs can become narrower so that theadjacent M1Cs can be bridged to each other. In an embodiment of thepresent invention, the depth (or height) of M1Cs is reduced, whereby theetching margin and bottom opening properties in the contact hole processfor forming M1Cs are improved and the occurrence of a bridge betweenM1Cs is effectively inhibited. Also, when the pattern pitch ofperipheral circuit wiring lines to which M1C is to be connected is only73 nm base on the minimum pitch, when M1C is connected to a peripheralcircuit wiring pattern having a small dimension, it can be connected toother peripheral circuit wiring patterns due to misalignment, thuscausing short circuits. In an embodiment of the present invention, theperipheral circuit wiring lines are not formed of a single layer, butare formed of a double layer, thus alleviating the problem of shorts inthe wiring patterns.

From the layout 10 of the peripheral circuit wiring lines designed as asingle layer as shown in FIG. 1, a layout 11 of first peripheral wiringlayer patterns as shown in FIG. 2 and a layout 15 of second peripheralcircuit wiring layers as shown in FIG. 4 are extracted. First peripheralcircuit wiring layer patterns 510 in FIG. 2 are introduced as a lowerlayer, and second peripheral circuit wiring layer patterns 550 areintroduced as an upper layer. Also, a layout 13 of interconnectioncontacts 530 as shown in FIG. 3 is extracted to connect the firstperipheral circuit wiring layer patterns 510 to the second peripheralcircuit wiring layer patterns 550 such that the first peripheral circuitwiring layer patterns 510 and the second peripheral circuit wiring layerpatterns 550 provide peripheral circuits (e.g., SA circuits) which havea layout having substantially the same as the layout 10 of theperipheral circuit wiring lines of FIG. 1. Such first peripheral circuitwiring layer patterns 510, second peripheral circuit wiring layerpatterns 550 and interconnection contacts 530 are formed to have adouble-layer structure, but are designed to constitute peripheralcircuits (e.g., SA circuits) which have a substantially same layout asperipheral circuits having the single-layer layout 10 of FIG. 1.

The peripheral circuit wiring lines are formed to have the double-layerstructure as described above, whereby the pattern pitch of the firstperipheral circuit wiring layer pattern 510 can be set at larger than104 nm based on the minimum pitch, and the pattern pitch of the secondperipheral circuit wiring layer pattern 550 can be set at larger than156 nm based on the minimum pitch. Thus, it is possible to effectivelyovercome problems which can occur due to a reduction in the patternpitch, such as short circuits or punch defects resulting from bridgingor misalignment. Furthermore, the interval between adjacentinterconnection contacts 530 can be set at 200 nm or more, unlike thecase in which the interval between MICs for peripheral circuit wiringlines having a single-layer structure is only 73 nm. Thus, theoccurrence of bridges between the contacts can be effectively inhibited.Also, as the pitch between the peripheral circuit wiring layer patterns510 and 550 is increased, the bit-line coupling capacitance can bereduced, and a mismatch of signals can also be reduced.

FIGS. 5 to 14 are cross-sectional views showing a semiconductor device,which comprises a capacitor and a double-layer metal contact, accordingto an embodiment of the present invention, and a method for fabricatingthe semiconductor device. Although embodiments of the present inventionare illustrated by example of a 30-nm technology node DRAM memorydevice, it can be applied not only to DRAM memory devices having smallertechnology nodes, but also when the height of metal contacts becomehigher and it is difficult to ensure an interval between metal contacts.

Referring to FIG. 5, a field layer 130 defining an active region 101 isformed on a semiconductor substrate 100 such as a silicon (Si) wafer.The field layer 130 can be formed by subjecting the semiconductorsubstrate 100 to a shallow trench isolation (STI) process. The STIprocess may form isolation trenches 110, forming a liner 120 consistingof a wall oxide layer, a silicon nitride (Si₃N₄) layer and a siliconoxide (SiO₂) layer in the trenches, and then a forming a silicon oxidelayer filling the isolation trenches 110. In the cell region of thesemiconductor device 100, cell transistors forming memory cells for DRAMdevices can be formed, and in a peripheral region surrounding the cellregion, peripheral circuit wiring lines and peripheral transistors,which constitute peripheral circuits such as sense amplifiers (SAs), canbe formed. The peripheral region can comprise a peripheral circuitregion or a core region.

Herein, the cell transistors (not shown) may have a buried gatestructure in order to ensure an increased channel length in a limitedsmall area resulting from a reduction in the design rule. In otherwords, the cell transistors may be formed to have a structure in which agate trench in which a gate is to be buried is formed across the activeregion 101 of the semiconductor substrate 100 and the cell gate isburied in the gate trench. In addition, in the peripheral region of thesemiconductor substrate 100, a peripheral gate 230 for a peripheraltransistor may be formed on a gate dielectric layer 210. The gate 230may be formed of either a double layer consisting of a poly-siliconlayer 231 and a tungsten layer 233 or a metal layer such as a titaniumnitride (TiN) or tungsten layer. On a sidewall of the peripheral gate230, a gate spacer 250 formed of an insulating layer such as siliconnitride may be attached, and on the gate 230, a gate capping layer 270may be formed of an insulating layer such as silicon nitride. Aprotective layer 330 that covers the gate capping layer 270 and the gatespacer 250 may be formed of an insulating layer such as silicon nitridein the form of a liner.

In the active region of the semiconductor substrate 100, a landing plug310 may be formed as a conductive layer such as a poly-silicon layer.The landing plug 310 may be formed either as an interconnection contactconnecting the active region to bit lines 410 or interconnectioncontacts which are connected to the storage nodes of the capacitor. Thislanding plug 310 electrically connects the bit lines 410 to the drain ofthe cell transistor in the cell region and electrically connects thestorage nodes of the capacitor to the source of the cell transistor.

On the resulting semiconductor substrate 100 on which the landing plug310 and the peripheral gate 230 were formed, a first interlayerinsulating layer 350 is formed. The first interlayer insulating layer350 may comprise an insulating layer such as silicon oxide. Bit lines410 that pass through the first interlayer insulating layer 350 so as tobe connected to some of the landing plugs 310 is formed using adamascene process. For example, the bit lines 410 are formed byrecessing the first interlayer insulating layer 350 to form damascenetrenches, forming a titanium nitride (TiN) layer as a barrier metallayer in the damascene trenches, and then forming a tungsten (W) layeron the barrier metal layer. Herein, on the sidewall of the bit lines410, bit line spacers (not shown) for ensuring lateral insulation fromstorage node contacts 610 may be further formed. Then, a bit linecapping layer 430 for insulating the upper side of the bit lines 410 maybe formed and the bit line capping layer 430 may comprise an insulatinglayer such as a silicon nitride layer. Then, storage node contacts 610that pass through the first interlayer insulating layer 350 of the cellregion so as to be connected to the landing plugs 310 may be formed by aself-aligned contact (SAC) process.

On the resulting semiconductor substrate 100 on which the bit lines 410and the storage node contacts 610 were formed, a first peripheralcircuit wiring layer pattern 510 is formed on the first interlayerinsulating layer 350. A first contact hole is formed, where the contactis aligned with the peripheral gate 230 to expose an upper surface ofthe gate 230, and a first peripheral circuit wiring layer filling thefirst contact hole is also formed. The first peripheral circuit wiringlayer can be formed by depositing a barrier metal (BM) layer comprisingtitanium/titanium nitride (Ti/TiN) and a tungsten layer on the barriermetal layer to fill the first contact hole. Herein, a chemicalmechanical polishing (CMP) for surface planarization of the tungstenlayer may be carried out. Then, a mask (not shown) having aconfiguration corresponding to the layout of the first peripheralcircuit wiring layer pattern 510 as shown in FIG. 2 is formed on thefirst peripheral circuit wiring layer, and an exposed portion of thefirst peripheral circuit wiring layer is selectively etched out to formthe first peripheral circuit wiring layer pattern 510. The portion ofthe first peripheral circuit wiring layer pattern 510 that fills thefirst contact hole is set as a first contact 512.

Referring to FIG. 6, a second interlayer insulating layer 710 coveringthe first peripheral circuit wiring layer pattern 510 is formed on thefirst interlayer insulating layer 350. It may be formed by depositing aninsulating material such as silicon oxide and then planarizing thedeposited material by CMP. Herein, a height or thickness of the secondinterlayer insulating layer 710 may be formed to a thicknesscorresponding to about 45-70% of a height of the storage node. Forexample, when the storage node is formed to a thickness of about 22000Å, the second interlayer insulating layer 710 may be formed to athickness of about 10000-15000 Å. Although not shown in the figures,before the second interlayer insulating layer 710 is deposited, a firstetch stopper covering the first peripheral circuit wiring layer pattern510 may be formed by depositing an insulating layer (such as a siliconnitride layer) having an etch selectivity with respect to silicon oxide.

A second contact hole 713 passing through the second interlayerinsulating layer 710 is formed using a mask (not shown) and an etchingprocess. Herein, the mask for the second contact hole 713 is formed tohave a configuration corresponding to the layout of the interconnectioncontacts 530 as shown in FIG. 3. The second contact hole 713 may beformed by selectively etching the portion of second interlayerinsulating layer 710 exposed through the mask. The second contact hole713 may be formed so as to correspond to the position of theinterconnection contact 530. Herein, the second contact hole 713 shouldbe aligned with the first contact hole or the portion of firstperipheral circuit wiring layer pattern 510 overlapping with the firstcontact hole, but the overlap can be somewhat misleading due tomisalignment. When the overlap margin is inadequate as described above,a first etch stopper (not shown) can be introduced, thereby preventingthe second contact hole 713 from exposing the underlying active region101 or the adjacent gate 230.

A second peripheral circuit wiring layer filling the second contact hole713 is deposited. For example, it can be formed by depositing a tungstenlayer on the second interlayer insulating layer 710 to fill the secondcontact hole 710 and subjecting the tungsten layer to CMP. Although notshown in the figure, a barrier metal layer comprising titanium nitride(TiN) may be formed, before the tungsten layer is deposited. A mask (notshown) having a configuration corresponding to the layout of the secondperipheral circuit wiring layer patterns 550 is formed on the secondperipheral circuit wiring layer, and the exposed portions of the secondperipheral circuit wiring layer are selectively etched out to form thesecond peripheral circuit wiring layer pattern 550. The portion of thesecond peripheral circuit wiring layer pattern that fills the secondcontact hole 713 is set as a second contact 530. The second contacts 530are set to correspond to the configuration of the interconnectioncontacts 530 as shown in FIG. 3.

Referring to FIG. 7, a portion of the second interlayer insulating layer710 (see FIG. 6) that was formed on the cell region is selectivelyremoved such that a remaining portion 711 of the second interlayerinsulating layer 710 that was formed on the peripheral region remains toform a remaining second insulating layer 711. For this purpose, a maskpattern 712 for exposing the cell region is formed on the secondinterlayer insulating layer 710, and the portion of second interlayerinsulating layer 710 exposed through the mask pattern 712 is selectivelyetched out, thereby exposing the upper surface of the storage nodecontacts 610 in the cell region.

Referring to FIG. 8, a second etch stopper 730 covering the secondperipheral circuit wiring layer pattern 550 is formed on the remainingsecond interlayer insulating layer 711. The second etch stopper 730 canbe formed by depositing an insulating layer such as a silicon nitridelayer, which has an etch selectivity with respect to silicon oxide, to athickness ranging from several ten Å or 200 Å to 1000 Å. The second etchstopper 730 isolates the remaining second interlayer insulating layer711 from the cell region to protect the remaining second interlayerinsulating layer 711 from a subsequent capacitor process.

Referring to FIG. 9, a mold layer 750 serving as a mold for imparting ashape to the storage nodes is formed on the second etch stopper 730. Thesecond etch stopper 730 can act as an etch stop point when the moldlayer 750 in the cell region is patterned and etched.

The mold layer 750 may be formed as a stack of a plurality of insulatinglayers which have different etch rates such that a through-hole which isto impart a shape to the storage node can be formed to have a sufficientdepth. For example, the mold layer 750 can be formed as a stackstructure comprising a phosphorous silicate glass (PSG) layer 751 havinga relatively high etch rate and a plasma-enhancedtetraethylorthosilicate (PE-TEOS) layer 753 having a relatively low etchrate. In some cases, the mold layer 750 may also be formed as a singlelayer of PSG or TEOS. This mold layer 750 may be formed to a thicknessthat provides a required height of the storage node, where the requiredheight is determined by considering the capacitor capacitance that is tobe achieved. For example, the mold layer 750 may be formed to athickness of 22000 Å or more.

A support layer may be formed on the mold layer 750. The support layer770 may support the sides of the upper portion of the storage nodes toprevent the storage nodes from falling down or leaning. The supportlayer 770 may comprise an insulating layer such as a silicon nitride(Si₃N₄) layer which has an etch selectivity with respect to the moldlayer 750. On the support layer 770, a protective capping layer 780 maybe formed in order to protect the support layer 770 in a subsequentetching process and may comprise a silicon oxide (SiO₂) layer.

Referring to FIG. 10, second though-holes 755 are formed which passthrough the protective capping layer 780, the support layer 770 and themold layer 750 to expose the underlying storage node contacts 610.Formation of such second through-holes 755 can be performed by aselective dry etching process. Then, storage nodes 810 are formed bydepositing a storage node layer to fill the through-holes 755 and thenplanarizing the deposited storage node layer by an etch back or CMPprocess. The storage nodes 810 may comprise a metal layer such as atitanium nitride (TiN). The storage node 810 is formed in a pillar shapefilling the through-hole 755. The storage node is difficult to form in acylindrical shape, because the depth of the through-hole 755 is 20000 Åor more and the size of the through-hole 755 is greatly reduced toincrease the aspect ratio.

Then, a portion of the protective capping layer 780 and the supportlayer 770 is selectively removed to form an opening 772 exposing aportion of the upper surface of the mold layer 750 (see FIG. 9). Theopening 772 may be formed such that it is located in the cell region,and during formation of the opening 772, a portion of the protectivecapping layer 780 and the support layer 770, which is located in theperipheral region, may be selectively removed. The opening 772 can beused as a channel into which a wet etching solution is introduced duringthe process of selectively removing a portion of the mold layer 750 toexpose an outer sidewall of the storage nodes 810.

Referring to FIG. 11, the portion of the mold layer 750 exposed throughthe opening 772 is removed by wet etching using an oxide etchingsolution such as BOE (buffer oxide etchant) or diluted hydrofluoric (HF)acid solution. The wet etching solution comes into contact with the moldlayer 750 through the opening 772 to remove a portion of the mold layer750, and subsequently the oxide etching solution is introduced tocontinuously remove a portion of the mold layer 750. This opening 772 isused as a channel for removing a portion of the mold layer 750 by wetetching and can be used as a channel into which a source is introducedduring a subsequent process of depositing a dielectric layer and a platenode layer.

In this wet etching process, the portion of the remaining secondinterlayer insulating film 711 formed on the peripheral region remainswithout being influenced by wet etching, because it has been isolatedfrom the cell region by the second etch stopper 730.

Referring to FIG. 12, a dielectric layer 830 is formed on the outersidewall of the storage nodes 810, and a plate node layer 850 isdeposited on the dielectric layer 830. Thus, a cell capacitor havingincreased capacitance resulting from the increased height of the storagenodes 810 is achieved. The dielectric layer 830 may be formed bydepositing a material having high dielectric constant (k), such aszirconium oxide (ZrO₂). Alternatively, the dielectric layer 830 may beformed as a composite layer of zirconium oxide-aluminum oxide(Al₂O₃)-zirconium oxide (ZAZ). The plate node layer 850 may be formed bydepositing titanium nitride (TiN) and tungsten (W). Because theremaining second interlayer insulating layer 711 is located as the lowerlayer on the peripheral region, a step height difference of the platenode layer between the cell region and the peripheral region can bereduced by about half compared to the case in which the remaining secondinterlayer insulating layer 711 is not present. Thus, in a subsequentprocess of patterning the plate node layer 850, improvement in theprocess margin can be achieved due to a reduction in the step height.

Referring to FIG. 13, a portion of the plate node layer 850 and thedielectric layer 830, which was formed in the peripheral region, isselectively removed. The portion of the plate node layer 850 thatoverlaps with the remaining portion of the second interlayer insulatinglayer 711 is selectively removed. Herein, a higher etching processmargin can be ensured due to the reduced step height difference, andthus the end of the patterned plate node 850 can be located closer tothe cell region. The etching process can stop on the second etch stopper730. Then, a third interlayer insulating layer 370 covering thepatterned plate node 850 is deposited on the exposed second etch stopper730.

Referring to FIG. 14, third contact holes 371 and 372 passing throughthe third interlayer insulating layer 370 are formed by a selectiveetching process. Specifically, a first hole 371 for third contacts,which is aligned with the second peripheral circuit wiring layer pattern550 or the second contact 530, and a second hole 372 for third contacts,which is connected to the plate node 850, may be formed. Such thirdcontact holes 371 and 372 have a depth corresponding to about half orless of the height of the storage nodes 810, because the remainingsecond interlayer insulating layer 711 is located under the thirdcontact holes. Thus, the occurrence of misalignment or the size of theholes can be reduced so that the interval between the third contactholes 371 and 372 can become wider. Thus, the step height of the platenode 850 can be reduced so that the end of the plate node 850 can belocated closer to the cell region, whereby the position of the thirdcontact hole 372 that is connected to the end of the plate node 850 canbecome closer to the cell region.

Then, third contacts 570 and 571 are formed by depositing conductivelayers, for example, a barrier metal layer of tungsten nitride and atungsten layer, to fill the third contact holes 371 and 372, andplanarizing the deposited conductive layers by CMP. The third contact570 is aligned with the second peripheral circuit wiring layer pattern550 or the second contact 530, so that the third contact 570 togetherwith the second contact 530 provides a metal contact (M1C) that connectsa first metal wiring line (M1) 900 to the semiconductor substrate 100 orthe peripheral gate 230. Because M1C consists of a stack of the secondcontact 530 and the third contact 570, an increase in the size of thecontact hole can be effectively inhibited, even though the total depth(or height) of M1C increases as the height of the storage node 810increases.

Thus, the interval between adjacent M1Cs, each consisting of the secondcontact 530 and the third contact 570, can be increased, so that anoccurrence of bridges between M1Cs resulting from the narrow intervalbetween the M1Cs can be effectively inhibited. Because M1C 530consisting of a stack of the contacts 530 and 570 allows a reduction inthe height of each of the second contact 530 and the third contact 570,which are actually formed, the depths of contact holes for the contactscan be reduced, thus ensuring an overlap margin. Thus, short circuitingor punch phenomena resulting from the misalignment M1C 530 and 570 canbe effectively prevented.

Also, because the third contact 571 can be located closer to the cellregion, the interval between the third contact 517 and the storage nodes810 or between M1C (consisting of the contacts 530 and 570) and thestorage nodes 810 can be reduced. Thus, the total size of asemiconductor chip comprising such metal contacts and storage nodes 810can be efficiently reduced.

After the third contacts 570 and 571 have been formed, first metalwiring lines (M1) 900 are formed on the third interlayer insulatinglayer 370. Such first metal wiring lines (M1) 900 serve as first-layerwiring lines (M1) in DRAM devices adopting a two-layer wiring linestructure consisting of first-layer and second-layer wiring lines, thatis, M1 and M2.

As described above, the present invention can provide a semiconductordevice comprising a capacitor and a metal contact and a fabricationmethod thereof, in which the height of the storage node can be increasedto higher capacitance while the occurrence of defects in the peripheralcircuit wiring lines and the metal contact can be effectively prevented.Also, the peripheral circuit wiring lines are formed to have adouble-layer structure, whereby the pattern pitch of the peripheralcircuit wiring lines in peripheral circuits such as sense amplifiers(SAs) can be increased so that the peripheral circuit wiring lines canbe patterned by a single patterning process without having to carry outa double patterning technology (DPT) process.

In addition, the wiring line patterns and metal contacts for the secondperipheral circuit wiring lines are formed at about half of the heightof the storage node, whereby the metal contacts can be formed to have amulti-layer stack structure consisting of a first metal contact and asecond metal contact. Thus, the margin of the process of forming each ofthe first and second metal contacts can be increased, and an increase inthe depth of contacts for the first and second metal contacts can beinhibited. Accordingly, the occurrence of bridges between adjacent metalcontact holes can be effectively inhibited to ensure a process margin,and the interval between the metal contact and the cell region can bereduced to reduce the design rule, thus reducing the size of the chip.

Embodiments of the present invention have been disclosed above forillustrative purposes only. Those skilled in the art will appreciatethat various modifications, additions and substitutions are possible,without departing from the scope and spirit of the invention asdisclosed in the accompanying claims.

1. A method for fabricating a semiconductor device comprising acapacitor and a double-layer metal contact, the method comprising:forming a second interlayer insulating layer on a cell region and aperipheral region; forming a second contact which passes through aportion of the second interlayer insulating layer on the peripheralregion; selectively removing a portion of the second interlayerinsulating layer on the cell region while allowing a portion of thesecond interlayer insulating layer on the peripheral region to remain;forming a mold layer covering both the portion of the cell region fromwhich the second interlayer insulating layer was removed and the secondcontact; forming storage nodes which pass through a portion of the moldlayer in the cell region; selectively removing the mold layer to exposethe storage nodes; forming a dielectric layer and a plate node, whichcover the exposed storage nodes; forming a third interlayer insulatinglayer covering the plate node; and forming third contacts which passthrough the third interlayer insulating layer so as to be connected tothe plate node and the second contact, respectively.
 2. The method ofclaim 1, wherein the method further comprises: forming a gate for aperipheral circuit on the peripheral region; forming a first interlayerinsulating layer covering the gate; forming bit lines which areinsulated by the portion of the first interlayer insulating layer on thecell region; forming storage node contacts which pass through the firstinterlayer insulating layer so as to be connected to the storage nodes,respectively; and forming on the portion of the first interlayerinsulating layer on the peripheral region a first contact which connectsthe second contact to the gate.
 3. The method of claim 1, whereinselectively removing the portion of the second interlayer insulatinglayer on the cell region comprises: forming on the second interlayerinsulating layer a mask pattern for exposing the cell region; andselectively etching out a portion of the second interlayer insulatinglayer exposed through the mask pattern.
 4. The method of claim 1,wherein the method further comprises: forming at an interface betweenthe mold layer and the remaining second interlayer insulating layer anetch stopper extending to cover the second peripheral circuit wiringlayer pattern, in which the etch stopper protects the second interlayerinsulating layer when the mold layer is removed.
 5. The method of claim4, wherein forming the dielectric layer and the plate node comprises:forming layers for the dielectric layer and the plate node so as toextend onto the etch stopper; and selectively etching out a portion ofthe dielectric layer for the plate node, which overlaps with theremaining portion of the second interlayer insulating layer, thuspatterning the plate node, in which the third contacts which areconnected to the plate node are located on the remaining portion of thesecond interlayer insulating portion.
 6. The method of claim 1, whereinthe method further comprises: forming on the mold layer a support layerfor supporting the storage nodes.
 7. A method for fabricating asemiconductor device comprising a capacitor and a double-layer metalcontact, the method comprising: forming a gate of a peripheraltransistor for a peripheral circuit on a peripheral region of asemiconductor substrate including a cell region and the peripheralregion; forming a first interlayer insulating layer covering the gate;forming a first contact and a first peripheral circuit wiring layerpattern, which are connected to the gate so as to constitute theperipheral circuit; forming a second interlayer insulating layercovering the first peripheral circuit wiring layer pattern; forming asecond contact and a second peripheral circuit wiring layer pattern,which pass through the second interlayer insulating layer so as toconstitute the peripheral circuit; selectively removing a portion of thesecond interlayer insulating layer on the cell region while allowing aportion of the second interlayer insulating layer on the peripheralregion to remain; forming a mold layer covering both a portion of thesemiconductor substrate from which the portion of the second interlayerinsulating layer was removed and the second peripheral circuit wiringlayer pattern; forming storage nodes that pass through a portion of themold layer in the cell region; selectively removing the mold layer toexpose the storage nodes; forming a dielectric layer and a plate node,which cover the exposed storage nodes; forming a third interlayerinsulating layer covering the plate node; and forming third contactsthat pass through the third interlayer insulating layer so as to beconnected to the plate node and the second peripheral circuit wiringlayer pattern, respectively.
 8. The method of claim 7, wherein theperipheral circuit comprises a sense amplifier that senses data to bestored in the storage nodes.
 9. The method of claim 7, wherein themethod further comprises: forming bit lines which are insulated by aportion of the first interlayer insulating layer on the cell region;forming storage node contacts which pass through the first interlayerinsulating layer so as to be connected to the storage nodes,respectively.
 10. The method of claim 9, wherein forming the bit linescomprises: forming damascene trenches in the first interlayer insulatinglayer; and forming the bit lines filling the damascene trenches.
 11. Themethod of claim 7, wherein forming the first peripheral circuit wiringlayer pattern comprises: obtaining a layout of the peripheral circuitwiring line for the peripheral circuit; extracting a layout of the firstperipheral circuit wiring layer pattern, a layout of the second contactand a layout of the second peripheral circuit from the layout of theperipheral circuit wiring line; forming a first contact hole exposingthe gate; forming the first peripheral circuit wiring layer, which fillsthe first contact hole, on the first interlayer insulating layer; andselectively etching the first circuit wiring layer so as to have aconfiguration corresponding to the layout of the first peripheralcircuit wiring layer pattern, thus forming the first contact and thefirst peripheral circuit wiring layer pattern.
 12. The method of claim7, wherein forming the second peripheral circuit wiring layer patterncomprises: forming the second contact hole, which passes through thesecond interlayer insulating layer, so as to have a configurationcorresponding to the layout of the second contact; forming the secondperipheral circuit wiring layer, which fills the second contact hole, onthe second interlayer insulating layer; and selectively etching thesecond peripheral circuit wiring layer so as to have a configurationcorresponding to the layout of the second peripheral circuit wiringlayer pattern, thus forming the second contact and the second peripheralcircuit wiring layer pattern.
 13. The method of claim 7, whereinselectively removing the portion of the second interlayer insulatinglayer on the cell region comprises: forming on the second interlayerinsulating layer a mask pattern for exposing the cell region; andselectively etching out a portion of the second interlayer insulatinglayer exposed through the mask pattern.
 14. The method of claim 7,wherein the method further comprises: forming at an interface betweenthe mold layer and the remaining second interlayer insulating layer anetch stopper extending to cover the second peripheral circuit wiringlayer pattern, in which the etch stopper protects the second interlayerinsulating layer when the mold layer is removed.
 15. The method of claim14, wherein the forming the dielectric layer and the plate nodecomprises: forming layers for the dielectric layer and the plate node soas to extend onto the etch stopper exposed by removal of the mold layer;and selectively etching out a portion of the dielectric layer for theplate node, which overlaps with the remaining portion of the secondinterlayer insulating layer, thus patterning the plate node, in whichthe third contacts which are connected to the plate node are located onthe remaining portion of the second interlayer insulating portion. 16.The method of claim 7, wherein the method further comprises: forming onthe mold layer a support layer for supporting the storage nodes.
 17. Asemiconductor device comprising: a cell region and a peripheral region;storage nodes formed in the cell region; a second contact passingthrough a second interlayer insulating layer formed on the peripheralregion; a dielectric layer and a plate node, which cover the storagenode and of which the end extends onto the second interlayer insulatinglayer; a third interlayer insulating layer covering the plate node andthe second interlayer insulating layer; and third contacts which passthrough the second interlayer insulating layer so as to be connected toboth a portion of the plate node on the second interlayer insulatinglayer and the second contact, respectively.
 18. The semiconductor deviceof claim 17, wherein the semiconductor device further comprises: a gateof a peripheral transistor formed on the peripheral region to constitutea peripheral circuit; a first interlayer insulating layer covering thegate; bit lines insulated by a portion of the first interlayerinsulating layer on the cell region; storage node contacts which passthrough the first interlayer insulating layer so as to be connected tothe storage nodes, respectively; and a first contact which passesthrough a portion of the first interlayer insulating layer on theperipheral region to connect the second contact to the gate.
 19. Thesemiconductor device of claim 18, wherein the semiconductor devicefurther comprises an etch stopper formed at an interface between thesecond and third interlayer insulating layers and extending onto thefirst interlayer insulating layer to support sides of the lower portionof the storage nodes and to isolate the storage nodes from the thirdinterlayer insulating layer.
 20. The semiconductor device of claim 17,wherein the semiconductor device further comprises a support layer whichsupports the upper portion of the storage nodes, where the storage nodesare formed in a pillar shape.
 21. A semiconductor device: asemiconductor substrate including a cell region and a peripheral region;a peripheral transistor and a gate, which are formed on the peripheralregion of the semiconductor substrate to constitute a peripheral region;a first interlayer insulating layer formed to cover the gate; a firstcontact and a first peripheral circuit wiring layer pattern, which areformed on a portion of the first interlayer insulating layer on theperipheral region so as to be connected to the gate and to constitutethe peripheral circuit; a second interlayer insulating layer formed onthe peripheral region to cover the first peripheral circuit wiring layerpattern; a second contact and a second peripheral circuit wiring layerpattern, which are formed to pass through the second interlayerinsulating layer so as to constitute the peripheral circuit; storagenodes formed on a portion of the first interlayer insulating layer inthe cell region; a dielectric layer and a plate node, which cover thestorage nodes and of which the end extends onto the second interlayerinsulating layer; a third interlayer insulating layer covering the platenode and the second interlayer insulating layer; and third contactswhich pass through the second interlayer insulating layer so as to beconnected to both a portion of the plate node on the second interlayerinsulating layer and the second peripheral circuit wiring layer pattern,respectively.
 22. The semiconductor device of claim 21, wherein theperipheral circuit comprises a sense amplifier which senses data to bestored in the storage nodes.
 23. The semiconductor device of claim 21,wherein the semiconductor device further comprises: bit lines insulatedby the portion of the first interlayer insulating layer in the cellregion; and storage node contacts which pass through the firstinterlayer insulating layer so as to be connected to the storage nodes,respectively.
 24. The semiconductor device of claim 21, wherein thesemiconductor device further comprises an etch stopper formed at aninterface between the second and third interlayer insulating layers andextending onto the first interlayer insulating layer to support thesides of a lower portion of the storage nodes and to isolate the storagenodes from the third interlayer insulating layer.
 25. The semiconductordevice of claim 21, wherein the semiconductor device further comprises asupport layer which supports an upper portion of the storage nodes. 26.The semiconductor device of claim 21, wherein the height of the secondcontact is 45-70% of the height of the storage node.